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Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard
http://hdl.handle.net/10173/747
http://hdl.handle.net/10173/747e3b631ce-620f-48e6-8183-0cbb1e00ace8
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IEICE_E93-D_1_33.pdf (1.6 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 公開日 | 2011-10-20 | |||||||||
| タイトル | ||||||||||
| タイトル | Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | analog circuit testing | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | circuit-under-test | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | IEEE 1149.4 standard | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | fault signature characterization | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| 著者 |
SAN-UM, Wimol
× SAN-UM, Wimol
× TACHIBANA, Masayoshi
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| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing. | |||||||||
| 書誌情報 |
IEICE Transactions on Information and Systems 巻 E93-D, 号 1, p. 33-42, 発行日 2010-01-01 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0916-8532@@@1745-1361 | |||||||||
| 書誌レコードID | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AA10826272@@@AA11510321 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1587/traninf.E93.D.33 | |||||||||
| 権利 | ||||||||||
| 権利情報 | Copyright © 2010 The Institute of Electronics, Information and Communication Engineers | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| 出版者 | ||||||||||
| 出版者 | The Institute of Electronics, Information and Communication Engineers | |||||||||
| 関係URI | ||||||||||
| 識別子タイプ | URI | |||||||||
| 関連識別子 | http://search.ieice.org/ | |||||||||
| 関連名称 | http://search.ieice.org/ | |||||||||
