{"_buckets": {"deposit": "11fa7e7b-f68c-439c-a36b-e2610ae87c76"}, "_deposit": {"created_by": 2, "id": "59", "owners": [2], "pid": {"revision_id": 0, "type": "depid", "value": "59"}, "status": "published"}, "_oai": {"id": "oai:kutarr.kochi-tech.ac.jp:00000059", "sets": ["5"]}, "author_link": ["212", "213"], "item_2_biblio_info_7": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2008-09", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "9-11", "bibliographicPageEnd": "1580", "bibliographicPageStart": "1575", "bibliographicVolumeNumber": "46", "bibliographic_titles": [{"bibliographic_title": "Microelectronics Reliability"}]}]}, "item_2_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "The novel method has been developed to detect accuracy fault\nelements in transistor level circuit, analyzing the characteristics of circuit\noperation influenced on leakage fault and being combined with diagnosis\nsoftware, based on switching level simulation. This method is based on behavior\nof CMOS transistor to which applied unstable voltage produced by leakage fault.\nUnsettled logic brings the transistor’s operation point to saturation area with\nmulti-impedance value and forms penetration current nets passing through it.\nOutput value on the net is calculated with each element impedance value and\nmiss-logic signal is spread to output terminal. An evaluation of this technology\ncorroborates to be precise method by using the circuit in which embedded\narbitrary fault portions.", "subitem_description_type": "Abstract"}]}, "item_2_publisher_35": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "Elsevier"}]}, "item_2_relation_13": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1016/j.microrel.2006.07.023", "subitem_relation_type_select": "DOI"}}]}, "item_2_rights_14": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "Copyright © 2006 Published by Elsevier Ltd."}]}, "item_2_source_id_11": {"attribute_name": "書誌レコードID", "attribute_value_mlt": [{"subitem_source_identifier": "AA00738419", "subitem_source_identifier_type": "NCID"}]}, "item_2_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "0026-2714", "subitem_source_identifier_type": "ISSN"}]}, "item_2_version_type_18": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_ab4af688f83e57aa", "subitem_version_type": "AM"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Sanada, M"}], "nameIdentifiers": [{"nameIdentifier": "212", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yoshizawa, Y"}], "nameIdentifiers": [{"nameIdentifier": "213", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2019-02-13"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "microrel_46_9-11_1575.pdf", "filesize": [{"value": "644.8 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 644800.0, "url": {"label": "microrel_46_9-11_1575.pdf", "url": "https://kutarr.kochi-tech.ac.jp/record/59/files/microrel_46_9-11_1575.pdf"}, "version_id": "93b8547e-9a8c-4af1-9c39-60572775203f"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Fault diagnosis technology based on transistor behavior analysis for physical analysis", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Fault diagnosis technology based on transistor behavior analysis for physical analysis"}]}, "item_type_id": "2", "owner": "2", "path": ["5"], "permalink_uri": "http://hdl.handle.net/10173/522", "pubdate": {"attribute_name": "公開日", "attribute_value": "2010-09-02"}, "publish_date": "2010-09-02", "publish_status": "0", "recid": "59", "relation": {}, "relation_version_is_last": true, "title": ["Fault diagnosis technology based on transistor behavior analysis for physical analysis"], "weko_shared_id": -1}