{"_buckets": {"deposit": "fd46f962-ebeb-48ad-b244-24df0651b949"}, "_deposit": {"created_by": 2, "id": "60", "owners": [2], "pid": {"revision_id": 0, "type": "depid", "value": "60"}, "status": "published"}, "_oai": {"id": "oai:kutarr.kochi-tech.ac.jp:00000060", "sets": ["5"]}, "author_link": ["214"], "item_2_biblio_info_7": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2008-08", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "8-9", "bibliographicPageEnd": "1538", "bibliographicPageStart": "1533", "bibliographicVolumeNumber": "48", "bibliographic_titles": [{"bibliographic_title": "Microelectronics Reliability"}]}]}, "item_2_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "A novel diagnosis method has been developed based on transistor operating point analysis. The method is worked by the way of fault logic propagation trace based on voltage value and the way of operation time setting of each gate circuit. The former way is to detect penetration current net result from fault, replace the net with impedance net, calculate voltage value of each node of the impedance net by OHM’s low, and then sequentially trace the fault logic propagation. The latter way is to set a standardized operation time at each gate circuit, and then, the virtual terminal is prepared at output point of gate unit. The proposed method makes it possible to detect not only signal propagation of each gate in order of time, but oscillation phenomenon brought by feedback fault.", "subitem_description_type": "Abstract"}]}, "item_2_publisher_35": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "Elsevier"}]}, "item_2_relation_13": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1016/j.microrel.2008.07.055", "subitem_relation_type_select": "DOI"}}]}, "item_2_rights_14": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "Copyright © 2008 Elsevier Ltd All rights reserved."}]}, "item_2_source_id_11": {"attribute_name": "書誌レコードID", "attribute_value_mlt": [{"subitem_source_identifier": "AA00738419", "subitem_source_identifier_type": "NCID"}]}, "item_2_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "0026-2714", "subitem_source_identifier_type": "ISSN"}]}, "item_2_version_type_18": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_ab4af688f83e57aa", "subitem_version_type": "AM"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Sanada, Masaru"}], "nameIdentifiers": [{"nameIdentifier": "214", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2019-02-13"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "microrel_48_8-9_1533.pdf", "filesize": [{"value": "408.8 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 408800.0, "url": {"label": "microrel_48_8-9_1533.pdf", "url": "https://kutarr.kochi-tech.ac.jp/record/60/files/microrel_48_8-9_1533.pdf"}, "version_id": "2c93299d-67a3-43fa-bd89-d2fbe01ebd25"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "Diagnosis", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Impedance", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Fault path tracing", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Transistor operating point analysis", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Voltage", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Voltage-based fault path tracing by transistor operating point analysis", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Voltage-based fault path tracing by transistor operating point analysis"}]}, "item_type_id": "2", "owner": "2", "path": ["5"], "permalink_uri": "http://hdl.handle.net/10173/523", "pubdate": {"attribute_name": "公開日", "attribute_value": "2010-09-02"}, "publish_date": "2010-09-02", "publish_status": "0", "recid": "60", "relation": {}, "relation_version_is_last": true, "title": ["Voltage-based fault path tracing by transistor operating point analysis"], "weko_shared_id": -1}